1. Field of the Invention
This invention relates generally to column-parallel single-slope analog-to-digital converters (ADCs), and more particularly to counter circuits used with such ADCs.
2. Description of the Related Art
Image sensors generally include an array of pixels arranged in rows and columns. One common approach to reading out the voltages produced by the pixels in each column is to use a column-parallel single-slope ADC. Such an ADC requires a ramp generator which generates a periodic voltage ramp signal and a comparator which toggles its output when the ramp voltage exceeds the column voltage being measured. A counter tracks the time that elapses between the start of the ramp and the comparator output toggling; this counter value, which is a digital representation of the column voltage, is latched and provided as the ADC's output.
A counter may be located in each column of a column-parallel single-slope ADC, or a single counter may be shared among multiple columns. An example of the latter case is shown in FIG. 1. A voltage from each column, Vin0, Vin1, . . . , Vinx is provided to an input of respective comparators 10, 12, 14, each of which also receives a shared (or ‘global’) voltage ramp Vramp produced by a ramp generator 16. During each ADC conversion cycle, Vramp increases linearly and covers the full input signal range. The output of each comparator toggles when Vramp exceeds its column voltage. The system includes a shared counter 18, and the columns include respective memory locations 20, 22, 24; when the output of each column's comparator toggles, the current counter value is stored in the column's memory location and is a digital representation of the column voltage.
One of the design challenges for column-parallel single-slope ADCs is to combine high resolution and fast conversion rate; achieving this requires high-speed counter operation. If there is one counter per column, then the capacitive load on the counter output bits is relatively small and thus high-speed operation is possible, but the power dissipation and substrate noise generated in each ADC column are significant. However, if a shared counter is used as shown in FIG. 1, then the capacitive load on the counter output bits is relatively large and thus its speed (or the number of ADC columns its output can be fed to) is limited.